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Memory architecture
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141	Review of last lecture  Architecture case studies  Memory performance is often the bottleneck  Parallelism grows with compute performance Add to Reading List Source URL: spcl.inf.ethz.ch Language: English - Date: 2015-10-04 17:36:16 Computer memory Transaction processing Computer architecture Concurrency control Compiler construction Memory ordering Consistency model Cache coherence Memory barrier Linearizability Schedule Sequential consistency
142	OPTIMIZATION AND PERFORMANCE MODELING OF STENCIL COMPUTATIONS ON MODERN MICROPROCESSORS‡ KAUSHIK DATTA†, SHOAIB KAMIL∗†, SAMUEL WILLIAMS∗†, LEONID OLIKER∗, JOHN SHALF∗, KATHERINE YELICK∗† Abstract. St Add to Reading List Source URL: crd.lbl.gov Language: English - Date: 2012-09-06 23:58:43 Computer architecture Cache Central processing unit Microprocessors Computer memory CPU cache Stencil code Loop nest optimization Opteron POWER5 Cell Multi-core processor
143	Moneta: A High-performance Storage Array Architecture for Next-generation, Non-volatile Memories Adrian M. Caulfield Arup De Rajesh K. Gupta Add to Reading List Source URL: mesl.ucsd.edu Language: English - Date: 2011-04-30 02:41:36 Computer memory Non-volatile memory Computer architecture Computer storage devices Computer storage media Solid-state drive IOPS Direct memory access PCI Express Flash memory CPU cache Noop scheduler
144	An Operational Semantics of Cache Coherent Multicore Architectures∗ Shiji Bijo, Einar Broch Johnsen, Ka I Pun, and S. Lizeth Tapia Tarifa University of Oslo, Norway {shijib, einarj, violet, sltarifa}@ifi.uio.no Add to Reading List Source URL: einarj.at.ifi.uio.no Language: English - Date: 2016-01-07 10:39:37 Cache coherency Parallel computing Computer architecture Computer memory computing CPU cache MSI protocol Coherent cache Cache MESI protocol Multi-core processor Draft:Cache memory
145	Flash Caching on the Storage Client David A. Holland, Elaine Angelino, Gideon Wald, Margo I. Seltzer Harvard University Abstract Flash memory has recently become popular as a caching Add to Reading List Source URL: www.eecs.harvard.edu Language: English Computer memory Computer architecture Non-volatile memory Cache Flashcache Solid-state drive ReadyBoost Flash memory Random-access memory Thrashing Write buffer CPU cache
146	Relaxed memory models must be rigorous ˇ c´ık3 Susmit Sarkar2 Francesco Zappa Nardelli1 Peter Sewell2 Jaroslav Sevˇ Luc Maranget1 Mark Batty2 Jade Alglave1 1 Add to Reading List Source URL: www0.cs.ucl.ac.uk Language: English - Date: 2012-09-10 07:41:00 Instruction set architectures Computer memory X86 architecture X86-64 Java memory model X86 Memory barrier Spinlock Memory ordering Low-level programming language Itanium ARM architecture
147	DimmWitted: A Study of Main-Memory Statistical Analytics Ce Zhang†‡ Christopher Re´ † † Add to Reading List Source URL: arxiv.org Language: English - Date: 2014-07-07 21:25:59 Parallel computing GraphLab Distributed computing architecture Learning Shard Replication Support vector machine Non-uniform memory access MapReduce Machine learning Artificial neural network Database
148	TACO0903-20 ACM-TRANSACTION September 14, 2012 Add to Reading List Source URL: www.des.udc.es Language: English - Date: 2014-06-30 07:11:02 Compiler optimizations Cache Computer memory Computer architecture CPU cache Central processing unit For loop Infinite loop
149	A Note on Distributed Computing Jim Waldo Geoff Wyant Ann Wollrath Sam Kendall Add to Reading List Source URL: ftp.surfnet.nl Language: English - Date: 1999-11-01 18:00:00 Distributed computing architecture Inter-process communication Object-oriented programming Parallel computing Component-based software engineering Distributed object Common Object Request Broker Architecture Object Remote procedure call Application programming interface Message passing Distributed shared memory
150	Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2015-12-01 06:21:41 Instruction set architectures Central processing unit Computer architecture Memory management Memory protection Capability-based security Pointer MIPS instruction set 64-bit computing Instruction set Reduced instruction set computing Kernel

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